{
    "2.5" : {
        "docs" : [
            { "CHANGELOG"    : "$BASEURL/CHANGELOG.TXT" }
        ],
        "components" : { 
            "fpga" : [ 
                {
                    "description": "FPGA",
                    "version" : "2.5",
                    "platform" : "UBGA256",                    
                    "hw_constraint" : { "fpga": { "max": 7 }},
                    "file": "$BASEURL/files/flx_aes3_256.rpd",
                    "md5": "c1cc1f63b46a9c865eacfbad77b62168",
                    "method": "fpgaflasher",
                    "connection": "uart-fpgaflash" 
                },
                {
                    "description": "FPGA",
                    "version" : "2.5",
                    "platform" : "UBGA484",                    
                    "hw_constraint" : { "fpga": { "min": 8 }},
                    "file": "$BASEURL/files/flx_aes3_484.rpd",
                    "md5": "acf0a37b4464bf5613ee5d92277ae642",
                    "method": "fpgaflasher",
                    "connection": "uart-fpgaflash" 
                }
            ]
        }
    }
}