{
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        "docs" : [
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        ],
        "components" : { 
            "fpga" : [ 
                {
                    "description": "FPGA",
                    "version" : "2.9",
                    "platform" : "UBGA256",                    
                    "hw_constraint" : { "fpga": { "max": 7 }},
                    "file": "$BASEURL/files/flx_aes3_256.rpd",
                    "md5": "487c0ec52be0a5bebc46a225d952489e",
                    "method": "fpgaflasher",
                    "connection": "uart-fpgaflash" 
                },
                {
                    "description": "FPGA",
                    "version" : "2.9",
                    "platform" : "UBGA484",                    
                    "hw_constraint" : { "fpga": { "min": 8 }},
                    "file": "$BASEURL/files/flx_aes3_484.rpd",
                    "md5": "a2ff124905f4b1a154c0578a5595e3f6",
                    "method": "fpgaflasher",
                    "connection": "uart-fpgaflash" 
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}