{
    "2.6-Beta1" : {
        "docs" : [
            { "CHANGELOG"    : "$BASEURL/CHANGELOG.TXT" }
        ],    
        "components" : {
            "fpga" : [ 
                {
                    "description": "FPGA",
                    "version" : "2.6",
                    "hw_constraint" : { "fpga": { "max": 7 }},
                    "file": "$BASEURL/files/flx_dante_256.rpd",
                    "md5":  "8497e276852edc4dd8252bb8f21d3086",
                    "method": "fpgaflasher",
                    "connection": "uart-fpgaflash" 
                }, 
                {
                    "description": "FPGA",
                    "version" : "2.6",
                    "hw_constraint" : { "fpga": { "min": 8 }},
                    "file": "$BASEURL/files/flx_dante_484.rpd",
                    "md5":  "3d6e9d5f6039674cbaba81123bf967ce",
                    "method": "fpgaflasher",
                    "connection": "uart-fpgaflash" 
                } 
            ],
            "dante" : [ 
                {
                    "description": "Dante",
                    "version" : "1.0.0",
                    "hw_constraint" : { "dante" : { "match" : "bkn2" } },
                    "file": "$BASEURL/files/FLX-DANTE-1.0.0-bkn2.dnt",
                    "md5":  "c3935d7d83b5837fd70f6ffe29ed889f",
                    "method": "danteflasher",
                    "connection": "telnet-danteflash"
                }, 
                {
                    "description": "Dante",
                    "version" : "1.0.0",
                    "hw_constraint" : { "dante" : { "match" : "bkn3" } },
                    "file": "$BASEURL/files/FLX-DANTE-1.0.0-bkn3.dnt",
                    "md5":  "bdaf967ff756ec1abb1dd633db3cca7d",
                    "method": "danteflasher",
                    "connection": "telnet-danteflash"
                } 
            ]
        }
    }
}