{
    "3.0" : {
        "docs" : [
            { "CHANGELOG"    : "$BASEURL/CHANGELOG.TXT" }
        ],    
        "components" : {
            "fpga" : [ 
                {
                    "description": "FPGA",
                    "version" : "3.0",
                    "hw_constraint" : { "fpga": { "min": 8 }},
                    "file": "$BASEURL/files/flx_dantesrc_484.rpd",
                    "md5":  "8816cfa67d1276e2c4a65c9c612dfbe5",
                    "method": "fpgaflasher",
                    "connection": "uart-fpgaflash" 
                } 
            ],
            "dante" : [ 
                {
                    "description": "Dante",
                    "version" : "1.0.1",
                    "hw_constraint" : { "dante" : { "match" : "bkn3" } },
                    "file": "$BASEURL/files/FLX-DANTESRC-1.0.1-bkn3.dnt",
                    "md5":  "cae92978ef0a959b48f32475fd174270",
                    "method": "danteflasher",
                    "connection": "telnet-danteflash"
                } 
            ]
        }
    }
}