{
    "3.2" : {
        "docs" : [
            { "CHANGELOG"    : "$BASEURL/CHANGELOG.TXT" }
        ],
        "components" : { 
            "fpga" : [ 
                {
                    "description": "FPGA",
                    "version" : "3.2",
                    "hw_constraint" : { "fpga": { "max": 7 }},
                    "file": "$BASEURL/files/flx_madi_256.rpd",
                    "md5": "d0b6716b903293ec485b9df83e7b587a",
                    "method": "fpgaflasher",
                    "connection": "uart-fpgaflash" 
                },
                {
                    "description": "FPGA",
                    "version" : "3.2",
                    "hw_constraint": { "fpga": { "min": 8 }},
                    "file": "$BASEURL/files/flx_madi_484.rpd", 
                    "md5": "f519b7b79b5de8a6bc1a03332271c0a9",
                    "method": "fpgaflasher",
                    "connection": "uart-fpgaflash" 
                }
            ]
        }
    }
}
