{
    "3.2-beta1" : {
        "docs" : [
            { "CHANGELOG"    : "$BASEURL/CHANGELOG.TXT" }
        ],
        "components" : { 
            "fpga" : [ 
                {
                    "description": "FPGA",
                    "version" : "3.2-beta1",
                    "hw_constraint": { "fpga": { "min": 8 }},
                    "file": "$BASEURL/files/FLX-MADISRC_3.2-beta1_484.rpd", 
                    "md5": "21a5a7c0c8197445ba3fc9bd6ecde742",
                    "method": "fpgaflasher",
                    "connection": "uart-fpgaflash" 
                }
            ]
        }
    }
}